The recent telecommunications revolution has led to an increased interest in wireless communications and, more specifically, to wireless applications in networking. This increased interest in wireless technology, coupled with the ever growing need for faster throughput speeds in networks, has put a premium on the radio electronics that are used to encode the data travelling between the different wireless nodes in a network. Part of every wireless device, be it a wireless telephone or a wireless transponder connected to a node in a wireless local area network (LAN), is a scrambler/descrambler device.
Scrambler/descrambler devices are quite well known and are currently in widespread use. They are used in wireless communications for not only security reasons but also for encoding the digital data to be transmitted. Internationally accepted design standards, such as the EEEE 802.11a standard for wireless communications, specify the polynomials to be used by compliant devices to help in standardizing wireless devices. However, the standards only provide a serial implementation of their scrambler/descrambler. Such an implementation is necessarily slow due to its serial nature.
Attempts have been made in the past to speed up the speed of such scrambler systems including increasing the clock speed of the circuit and using pseudo parallel methods. However, such attempts are fraught with drawbacks including increased power consumption, problems with thermal issues and synchronization issues.
Based on the above a truly parallel solution is required. Such a solution should not only provide the advantages of parallel circuits such as increased volume in output but should also provide easy scalability and adaptability to the differing implementations and standards.
It is therefore an object of the present invention to provide alternatives to the prior art which will, if not overcome, at least mitigate the drawbacks of the prior art.